Generation of new power processing structures exploiting genetic programming

This paper describes the use of genetic algorithms to generate power processing circuits. In order to speed up the algorithm, the fitness of the circuits is evaluated using an explicit integration method based on the 4th order Adams–Bashforth formula. Different combinations of genetic primitives for the crossover and mutation processes have been tested. The algorithm is demonstrated by generating new structures of voltage multipliers, which specifically focus on energy harvesting systems. These systems require low input voltages, usually under the diode threshold value. The Adams–Bashforth method allows to achieve a simulation time that is about five times faster than that of SPICE-based simulations.This work was partially funded by Spanish government project TEC2015-66878-C3-2-R (MINECO/FEDER, UE)

Stability and efficiency of explicit integration in interconnect analysis on GPUs

This paper presents a technique to parallelise a numeric integration solver on general purpose GPU. The technique is based on the combination of space state modeling with an explicit integration method based on the Adams-Bashforth second order formula. The paper studies the stability of variable step explicit method and proposes a technique to guarantee integration stability using this technique. Although explicit methods require smaller integration steps compared to the traditional implicit techniques, they avoid the complex calculations on large which are used to solve the last ones. The technique is demonstrated simulating an RC model of an VLSI interconnect. Results achieved by the proposed variable step explicit method is compared to those achieved by a traditional implicit integration based simulator like Ngspice. The results show that the parallelised explicit solution is one order of magnitude faster than the implicit one for increasingly complex circuits.This work has been partially funded by Spanish government through project RTI2018-097088-B-C33 (MINECO/FEDER, UE) and by EPSRC (the UK Engineering and Physical Sciences Research Council) under grant EP/N0317681/1. The research stay at The University of Southampton has been supported by Fundacion Séneca-Agencia de Ciencia y Tecnología de la Región de Murcia, Programa Regional de Movilidad, Colaboración e Intercambio de Conocimiento Jimenez de la Espada under grant 21187/EE/1

High-speed analog simulation of CMOS vision chips using explicit integration techniques on many-core processors

This work describes a high-speed simulation technique of analog circuits which is based on the use of statespace equations and an explicit integration method parallelised on a multiprocessor architecture. The integration step of such method is smaller than the one required by an implicit simulation technique based on Newton–Raphson iterations. However, given that explicit methods do not require the computation of time-consuming matrix factorizations, the overall simulation time is reduced. The technique described in this work has been implemented on a NVIDIA general purpose GPU and has been tested simulating the Gaussian filtering operation performed by a smart CMOS image sensor. Such devices are used to perform computation on the edge and include built-in image processing functions. Among those, the Gaussian filtering is one of the most common functions, since it is a basic task for early vision processing. These smart sensors are increasingly complex and hence the time required to simulate them during their design cycle is also larger and larger. From a certain imager size, the proposed simulation method yields simulation times two order of magnitude faster that an implicit method based tool such us SPICEThis work has been partially funded by Spanish government through project RTI2018-097088-B-C33 (MINECO/FEDER, UE) and by EPSRC (the UK Engineering and Physical Sciences Research Council) under grant EP/N0317681/1. The research stay at University of Southampton (UK) has been supported by Ministerio de Educación, Cultura y Deporte within the “Programa Estatal de Promoción del Talento y su Empleabilidad en I+D+i, Subprograma Estatal de Movilidad, del Plan Estatal de I+D+I” under grant PRX18/00565

Simulation acceleration of image filtering on CMOS vision chips using many-core processors

This paper describes an efficient numerical solution to speed up transient simulations of analog circuits on a many-core computer. The technique is based on an explicit integration method, parallelised on a multiprocessor architecture. Although the integration step is smaller than the required one by traditional simulation methods based on Newton–Raphson iterations, explicit methods do not require to compute complex calculations such us matrix factorizations, which lead to long CPU simulation times. The proposed technique has been implemented on a NVIDIA GPU and has been demonstrated simulating Gaussian filtering operations performed by a CMOS vision chip. These type of devices, which are used to perform computation on the edge, include built-in image processing functions, turning them into very complex and time consuming circuits during their design. The proposed method is faster that Ngspice for different image sizes, and for 128 x 128 pixels image size it achieves a speed up of two orders of magnitude.This work has been partially funded by Spanish government through project RTI2018-097088-B-C33 and by EPSRC (the UK Engineering and Physical Sciences Research Council) under grant EP/N0317681/1. The research stays at University of Southampton (UK) have been supported by Ministerio de Educación, Cultura y Deporte within the “Programa Estatal de Promoción del Talento y su Empleabilidad en I+D+i, Subprograma Estatal de Movilidad, del Plan Estatal de I+D+I” under grant PRX18/00565 and by Universidad Politécnica de Cartagena - Campus de Excelencia Internacional Mare Nostru

Multiple adaptive neuro-fuzzy inference systems for accurate microwave CAD applications

An approach for applying fuzzy logic for accurate CAD of microwave circuits is presented. Our proposed method combines space-mapping (SM) technology and multiple adaptive neuro-fuzzy inference systems (MANFIS) for the modeling of microwave devices. MANFIS is trained to predict a nonlinear vector multidimensional mapping function, which is obtained from SM approach. Optimization by micro-genetic algorithm is used to find nonlinear vector multidimensional mapping function for singular systems. This approach is applied to a shielded microstrip line within a region of interest. The parameter values (ε reff ( f ) , Zc ( f )) computed with our proposed method are in excellent agreement with those obtained from electromagnetic simulations

Influence of the amplifier sharing tecnique in pipeline analog-to digital converters (ADCs)

Three 12 bit, 40 MS/s pipelined analog-to-digital-converters (ADCs) are developed in 0.35μm CMOS process with 3.3V single power supply. The proposed ADCs architectures study the influence of the amplifier sharing technique in the power consumption and the main performances in the pipeline ADCs. Simulations results with extracted netlists are provided and show that the amplifier sharing technique has potential to be used in the reduction of the power consumption.This work has been partially supported by Ministerio de Educación y Ciencia of Spain (TIN2006-15460-C04-04)

A library-based tool to translate high level DNN models into hierarchical VHDL descriptions

This work presents a tool to convert high level models of deep neural networks into register transfer level designs. In order to make it useful for different target technologies, the output designs are based on hierarchical VHDL descriptions, which are accepted as input files for a wide variety of FPGA, SoC and ASIC digital synthesis tools. The presented tool is aimed to speed up the design and synthesis cycle of such systems and provides the designer with certain capability to balance network latency and hardware resources. It also provides a clock domain crossing to interface the input layer of the synthesized neural networks with sensors running at different clock frequencies. The tool is tested with a neural network which combines convolutional and fully connected layers designed to perform traffic sign recognition tasks and synthesized under different hardware resource usage specifications on a Zynq Ultrascale+ MPSoC development board.This work has been partially funded by Spanish Ministerio de Ciencia e Innovación (MCI), Agencia Estatal de Investigación (AEI) and European Region Development Fund (ERDF/FEDER) under grant RTI2018-097088-B-C33

A low kickback fully differential dynamic comparator for pipeline analog-to-digital converters

This study presents a fully differential dynamic comparator with low kickback noise, an effect caused by voltage variations in the regeneration nodes of these types of circuit. Given their low power dissipation, dynamic comparators are key circuits in analog-to-digital converters (ADCs), especially in pipelined ADCs. The proposed comparator has been simulated and compared with three other comparator topologies. The value of the kickback noise generated by the proposed circuit is lower than that generated by other conventional dynamic comparators over a wide input range, while simultaneously showing a low offset voltage error. The dynamic comparator has been implemented in a low-resolution ADC with a resolution of 2.5 effective bits, which has been prototyped in a 0.35-m CMOS AMS C35B4 process. Its size is 34 m × 38 m.This work has been partially funded by Spanish government projects TEC2015‐66878‐C3‐2‐R (MINECO/FEDER, UE) and RTI2018‐097088‐B‐C33 (MINECO/FEDER, UE)

An 11-bit 20-MSample/s pipelined ADC with OTA bias current regulation to optimize power dissipation

This paper presents a pipeline analog to digital converter (ADC) consisting of five stages with 2.5 effective bit resolution. Several techniques were combined for the reduction of the power consumption and to preserve the converter linearity. To reduce the power consumption, the circuit has two scaled operational transconductance amplifiers (OTAs), which are shared by the first four pipeline stages. The last fifth stage is a single decoder with 2.5 effective bits. Each OTA includes additional circuitry to adapt the power consumption according to the stage that uses the OTA. This technique changes the bias current depending on the stage in operation. The ADC was optimized to obtain 11-bit resolution with frequencies from 1 kHz to 10 MHz. The technology used to simulate the ADC is a 3.3 V 0.35 μm CMOS process and the circuit consumes 17.9 mW at 20 MSample/s sampling rate. With this resolution and sampling rate, it achieves 67.28 dB SNDR and 10.88 bit ENOB at 0.1 MHz input frequency. The Figure of Merit is 0.473 pJ/stepThis work has been partially funded by Spanish government project TEC2015-66878-C3-2-R (MINECO/FEDER, UE)

Comparative analysis of two operational amplifier topologies for a 40MS/s 12-bit pipelined ADC in 0.35μm CMOS

This paper describes a comparative analysis between two topologies of operational amplifiers to design a 40 MS/s 12-bit pipeline analog to digital converter (ADC). The analysis includes AC and transient simulation to select the proper topology. This ADC is implemented in a 0.35 mum AMS CMOS technology with 3.3 V single power supply. The capacitors and selected operational amplifiers were scaled for low power dissipation. All analog components of this pipeline ADC are fully differential, as there are dynamic comparators, analog multiplexers and operational amplifiers with gain boosting.This work has been partially supported by Fundación Séneca of Región de Murcia(Ref:03094/PI/05)and MEC of Spain(Ref:TIN2006-15460-C04-04)